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intel_registers [PHCwiki]
 

The following documentation is a summary of the things we found in the Internet and found out by ourself. There is no guarantee that those informations are correct.

 MSR Map

Most of those BITs are self-declaring.

HALF adds 0.5 to the given FID. If for example FID is 9 and HALF is set, the used FID is 9.5.

SLFM (Super Low Frequency Mode aka Dynamic FSB) is halving the internal BUS frequency. If the Bit is set the CPU is skipping every second cycle of the FSB. Some CPU's are able to multiply with half integers.

 
 
intel_registers.txt · Last modified: 2010/01/17 13:32 by thefallen
 
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